Method for signal transmission, circuit and memory

ABSTRACT

A circuit for signal transmission, memory, and method for signal transmission are provided. The circuit includes: a signal processing circuit, configured to receive an input first signal, obtain a second signal by processing the first signal in a preset processing manner, and take the second signal as an output signal of the signal processing circuit; and a selection circuit, configured to receive the input first signal, the second signal and a control signal, and take the first signal or the second signal as an output signal of the selection circuit according to the control signal.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority toChinese Patent Application No. 202110579192.6, filed on May 26, 2021,the contents of which are incorporated herein by reference in theirentirety for all purposes.

BACKGROUND

A memory is a device for storing data which is commonly used in anelectronic device. Taking a Dynamic Random Access Memory (DRAM) as anexample, the DRAM uses the principle of the semiconductor memory toindicate that a binary bit is 1 or 0 by the amount of the electricalcharges storied in a capacitor.

In the related art, with the development of the semiconductor process,the operating frequency that can be implemented by the DRAM is gettinghigher and higher, and there are more and more analog and digitaldevices in the DRAM itself and the platform on which the DRAM islocated, such that the received external signal is susceptible to beinterfered by other devices when the DRAM is operating, which in turncauses that the narrow pulse is generated on the received externalsignal and the accuracy of the subsequent processing for the externalsignal by the DRAM will be affected.

Therefore, how to eliminate the narrow pulse of the external signalreceived by the memory is a technical problem to be solved in the art.

SUMMARY

The present disclosure provides a method for signal transmission, acircuit and a memory to implement elimination of narrow pulse of theexternal signal received by the memory.

A first aspect of the present disclosure provides a circuit for signaltransmission. The circuit comprises a signal processing circuit and aselection circuit. The signal processing circuit is configured toreceive an input first signal, obtain a second signal by processing thefirst signal in a preset processing manner, and take the second signalas an output signal of the signal processing circuit. The selectioncircuit is configured to receive the input first signal, the secondsignal and a control signal, and take the first signal or the secondsignal as an output signal of the selection circuit according to thecontrol signal.

A second aspect of the present disclosure provides a memory includingthe circuit for signal transmission, the circuit comprising: a signalprocessing circuit, configured to receive an input first signal, obtaina second signal by processing the first signal in a preset processingmanner, and take the second signal as an output signal of the signalprocessing circuit; and a selection circuit, configured to receive theinput first signal, the second signal and a control signal, and take thefirst signal or the second signal as an output signal of the selectioncircuit according to the control signal.

A third aspect of the present disclosure provides a method for signaltransmission. The method can be performed by the circuit for signaltransmission provided in the first aspect. The method includes:acquiring a control signal and a first signal; and outputting the firstsignal according to the control signal, or obtaining a second signal byprocessing the first signal in a preset processing manner, andoutputting the second signal.

BRIEF DESCRIPTION OF THE DRAWINGS

To explain the embodiments of the present disclosure or the technicalsolutions in the related art more clearly, references will now be madebriefly to the accompanying drawings required for the embodiments or therelated art. It will be apparent that the accompanying drawings in thefollowing description are only some of the embodiments of the presentdisclosure, and other drawings may be obtained to those skilled in theart based on these accompanying drawings without involving any inventiveefforts.

FIG. 1 is a schematic diagram of an application scenario according tothe present disclosure.

FIG. 2 is a schematic diagram of the waveform of the external signalreceived by a memory.

FIG. 3 is a schematic structural diagram of an embodiment of a memoryaccording to the present disclosure.

FIG. 4 is a schematic structural diagram of an embodiment of a circuitfor signal transmission according to the present disclosure.

FIG. 5 is a schematic diagram of the waveform of an embodiment of asignal processed by a signal processing circuit according to the presentdisclosure.

FIG. 6 is a schematic structural diagram of another embodiment of acircuit for signal transmission according to the present disclosure.

FIG. 7 is a schematic diagram of the waveform of another embodiment of asignal processed by a signal processing circuit according to the presentdisclosure.

FIG. 8 is a schematic structural diagram of another embodiment of acircuit for signal transmission according to the present disclosure.

FIG. 9 is a schematic structural diagram of another embodiment of acircuit for signal transmission according to the present disclosure.

FIG. 10 is a schematic structural diagram of a shift register accordingto the present disclosure.

FIG. 11 is a schematic diagram of the waveform of the respective signalstransmitted by various units in a circuit for signal transmissionaccording to the present disclosure.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present disclosurewill be described clearly and completely below with the reference of theaccompanying drawings in the embodiments of the present disclosure. Itwill be apparent that the embodiments described herein are only a partof the embodiments of the present disclosure, rather than all theembodiments of the present disclosure. Based on the embodiments inpresent disclosure, all other embodiments obtained by those skilled inthe art without involving inventive effort shall fall within the scopeof the present disclosure.

The terms “first”, “second”, “third”, and “fourth”, etc. (if any) in thedescription and claims of the present disclosure and the above-mentionedaccompanying drawings are used to distinguish similar objects, and arenot necessarily used to describe a specific sequence or order. It is tobe understood that data used in this way may be interchangeable underappropriate cases so that the embodiments of the present disclosuredescribed herein can be implemented, for example, in an order other thanthose illustrated or described herein. In addition, the terms “include”and “have” as well as any variations thereof are intended to covernon-exclusive inclusions. For example, processes, methods, systems,products, or devices that include a series of steps or units are notnecessarily limited to those steps or units clearly listed, but mayinclude other steps or units that are not clearly listed or are inherentto these processes, methods, products, or devices.

FIG. 1 is a schematic diagram of an application scenario of the presentdisclosure. A manner of receiving an external signal by a memory 1 isillustrated as in FIG. 1 . Here, an interface 10 built in the memory 1may be configured to receive an external signal, and transmit thereceived external signal into the memory 1 to be processed.

In some embodiments, the processing circuit 11 may be a logic circuithaving a signal processing capability, or the like. Then the externalsignal received by the memory 1 may be directly sent to the processingcircuit 11 in the memory 1, and the processing circuit 11 performssubsequent processing on the external signal. The specific processing onthe external signal performed by the processing circuit 11 is notlimited herein.

In some embodiments, the interface 10 may be a physical device (e.g., achip, a circuit, a logic circuit, etc. for receiving a signal)configured for the memory 1 for receiving the external signal. In someother embodiments, the interface 10 may be a virtual module fordepicting FIG. 1 . For example, the processing circuit 11 may receivethe external signal through one of its pins or a connected wire, and thepin or wire for receiving the external signal may be abstracted as theinterface 10 in FIG. 1 .

FIG. 2 is a schematic diagram of the waveform of an external signalreceived by a memory. Herein, it is assumed that the memory 1illustrated in FIG. 1 is receiving the signal {circle around (1)}transmitted from an external device connected to the memory 1. In FIG. 2, taking the signal {circle around (1)} being a standard square wavesignal with cycle T as an example, since the signal {circle around (1)}can be understood as a signal actually transmitted by the externaldevice without any change or interference, and is also in a form whichis desired to be received by the memory 1, the signal {circle around(1)} can be denoted as a purpose signal. However, during the actualoperation of the memory, the received external signal is easilyinterfered by other devices, which leads to generation of a narrow pulseon the external signal received by the memory. For example, although theexternal device sends the signal {circle around (1)} to the memory 1 asillustrated in FIG. 1 , the external signal actually received by thememory 1 is the signal {circle around (2)} having a waveform with theglitch, such that the signal {circle around (3)} having a narrow pulseis obtained after that the processing circuit 11 of the memory 1 smoothsthe signal {circle around (2)}. Thus, the signal that should beprocessed by the processing circuit 11 is the signal {circle around(1)}, but the signal that actually be processed by the processingcircuit 11 is the signal {circle around (3)} due to the problem of theexternal signal reception. The narrow pulse in the signal {circle around(3)} will affect the normal operation of the processing circuit 11 andreduce the accuracy of processing the signal by the processing circuit11.

Accordingly, the present disclosure further provides a method for signaltransmission, a circuit, and a memory for eliminating the narrow pulseof the external signal received by the memory, so that the narrow pulseof the external signal will not affect normal processing on the externalsignal within the memory and improve the accuracy of processing thesignal by the memory.

The technical solutions of the present disclosure will be described indetail with specific embodiments. The following specific embodiments maybe combined with each other, and the same or similar concepts orprocesses may not be elaborated in some embodiments.

FIG. 3 is a schematic structural diagram of a memory according to anembodiment of the present disclosure. On the basis of the embodiment asillustrated in FIG. 1 , the memory as illustrated in FIG. 3 furtherincludes a circuit 12 for signal transmission between the interface 10and the processing circuit 11, so that the external signal, which isreceived by the memory 1 through the interface 10, is processed by thecircuit 12 for signal transmission and then sent to the processingcircuit 11 inside the memory for subsequent processes.

FIG. 4 is a schematic structural diagram of an embodiment of a circuitfor signal transmission according to the present disclosure. FIG. 4illustrates a specific implementation of the circuit 12 for signaltransmission as illustrated in FIG. 3 . The circuit 12 for signaltransmission specifically includes a signal processing circuit 121 and aselection circuit 122.

The signal processing circuit 121 is configured to receive an externalsignal (denoted as a first signal or External Signal, etc.), obtain asecond signal (denoted as Internal Signal, or the like) by processingthe first signal in a preset processing manner, and output the secondsignal to the selection circuit 122 as an output signal of the signalprocessing circuit 121.

In some embodiments, specifically, the signal processing circuit 121 maybe configured to remove a narrow pulse signal between two adjacentpulses in the first signal. This process may also be understood assmoothing the signal between adjacent effective square wave pulsesignals in the first signal. For example, FIG. 5 is a schematic diagramof the waveform of a signal processed by a signal processing circuitaccording to an embodiment of the present disclosure. Herein, the signalprocessing circuit 121 receives a signal {circle around (4)} asillustrated in FIG. 5 , keeps the first pulse and the second pulse,which are effective pulse signals, in the signal {circle around (4)}unchanged, and removes the narrow pulse, which is generated due to thetransmission glitch, between the first pulse and the second pulse, sothat a low level between the first pulse and the second pulse can bekept, thereby obtaining a signal {circle around (5)}, and the signalprocessing circuit 121 outputs the signal {circle around (5)} to theselection circuit 122 as a second signal. As illustrated in FIG. 5 , thepulse signal being a high level is taken as an example. Accordingly, itis to be understood that, if the pulse signal of the first signal is thelow level, the signal processing circuit 121 can also keep the signalbetween two active low-level square wave pulses at high level, therebyobtaining the second signal that the narrow pulse has been eliminated.

The selection circuit 122 may be configured to receive a first signalinput from the external of the memory and receive a second signal fromthe signal processing circuit 121. In this case, the selection circuit122 may select a signal from the first signal and the second signal,that is, the selection circuit 122 may select the first signal or thesecond signal as an output of the selection circuit 122. In this case,the output signal of the selection circuit 122 is the output signal ofthe circuit 12 for signal transmission. The selection circuit 122 mayselect a signal from the first signal and the second signal according tothe control signal. The control signal may be sent by the controlcircuit of the memory. In a specific implementation, the selectioncircuit 122 may be a data multiplexer (MUX).

In some embodiments, FIG. 6 is a schematic structural diagram of anotherembodiment of the circuit for signal transmission according to thepresent disclosure. In an example as illustrated in FIG. 6 , the controlcircuit 123 may be arranged in the circuit 12 for signal transmission tosend a control signal (denoted as TM_Block, etc.) to the selectioncircuit 122, such that the selection circuit 122 outputs the firstsignal or the second signal according to the control signal.Alternatively, in some other embodiments, the control circuit 123 may bearranged before the circuit 12 for signal transmission, for example, theprocessing circuit 11 in the memory 1. Alternatively, the controlcircuit 123 may be another circuit in the memory 1 that can beconfigured to send a control signal to the selection circuit 122.Alternatively, the control circuit 123 may be a circuit other than thememory 1.

Then, the selection circuit 122 may determine the first signal or thesecond signal as an output signal according to the received controlsignal. For example, when the control signal received by the selectioncircuit 122 corresponds to a first state, the received second signal isoutput as an output signal. When the control signal received by theselection circuit 122 corresponds to the second state, the receivedfirst signal is output as an output signal. Herein, the first state andthe second state may be different level states of the control signal.For example, the first state may be that the control signal is highlevel, and the second state may be that the control signal is low level,etc.

In some embodiments, the signal processing circuit 121 may also receivethe control signal and obtains the second signal by processing the firstsignal in the preset manner only when the control signal corresponds tothe first state. When the received control signal corresponds to thesecond state, since the selection circuit 122 outputs the first signal,the signal processing circuit 121 can output a fixed value as the secondsignal without processing the first signal, thereby reducing redundancycalculation and energy consumption.

In some embodiments, the control circuit 123 may send the control signalwith different states to the selection circuit 122 according todifferent conditions. For example, when the control circuit 123determines that a current condition meets a trigger condition, in thiscondition, it indicates that a narrow pulse may occur in the externalsignal received by the memory, and then the control circuit 123 sendsthe control signal with the first state to the selection circuit 122.The control signal with the second state is sent to the selectioncircuit when the control circuit 123 determines that the current casedoes not meet the trigger condition and the possibility that a narrowpulse occurs in the external signal is low. In another specificimplementation scenario, when the memory is in a test state, the controlcircuit 123 may send a control signal with the first state to theselection circuit, and when the memory is in a normal operation state,the control circuit sends a control signal with the second state to theselection circuit.

Exemplarily, the circuit 12 for signal transmission illustrated in FIG.6 receiving the signal {circle around (4)} illustrated in FIG. 5 istaken as an example. At this case, since the signal {circle around (4)}has a narrow pulse, the control circuit 123 transmits a control signalwith the first state to the selection circuit 122. The signal processingcircuit 121 obtains the signal {circle around (5)} according to thesignal {circle around (4)} and inputs the signal {circle around (5)} asa second signal to the selection circuit 122. The selection circuit 122receives the signal {circle around (4)} and the signal {circle around(5)} at the same time and take the signal {circle around (5)} as theoutput signal of the selection circuit.

Exemplarily, FIG. 7 is a schematic diagram of the waveform of the signalprocessed by the signal processing circuit according to anotherembodiment of the present disclosure. FIG. 8 is a schematic structuraldiagram of the circuit for signal transmission according to anotherembodiment of the present disclosure. As an example, the circuit 12 forsignal transmission illustrated in FIG. 8 receives the signal {circlearound (6)} illustrated in FIG. 7 . As there is no narrow pulse in thesignal {circle around (6)}, the control circuit 123 sends the controlsignal with the second state to the selection circuit 122. The selectioncircuit 122 selects the signal {circle around (6)} as the output signalof the selection circuit 122 according to the control signal with thesecond state. Further, in the state as illustrated in FIG. 8 , thesignal processing circuit 121 may not output the second signal to theselection circuit 122 according to the received control signal.

In some embodiments, FIG. 9 is a schematic structural diagram of thecircuit for signal transmission of another embodiment of the presentdisclosure. FIG. 9 illustrates a specific implementation of the signalprocessing circuit 121 in the circuit 12 for signal transmission. Thesignal processing circuit 121 as illustrated in FIG. 9 specificallyincludes a shift register 1211, a latch 1212, and a logic processingsubcircuit 1213.

The shift register 1211 is configured to receive the first signal andthe clock signal, shift the first signal according to the clock cycle ofthe first signal, and output the shifted first signal to the latch 1212.In some embodiments, FIG. 10 is a schematic structural diagram of ashift register according to the present disclosure. The shift register1211 illustrated in FIG. 10 specifically includes an N-bit serial shiftregister. N is the number of first clocks corresponding to a cycle ofthe first signal. As illustrated in FIG. 10 , one block graph representsone shift register. Each input D receives a front-end input signal and aCLK clock signal. Q outputs signal to the next stage. In particular, theinput D of the first shift register of the N-bit serial shift registerreceives the first signal.

In some embodiments, the output end of the N-bit serial shift registernot only outputs a second shifted signal by shifting the first signal byN bits to the subsequent latch 1212, but also outputs a first shiftedsignal by shifting the first signal by M bits to the latch 1212. M is anumber of second clocks corresponding to the pulse length of the firstsignal.

The above process will be described with reference to FIG. 11 . FIG. 11is a schematic diagram of the waveform of the respective signaltransmitted by each unit in the circuit for signal transmissionaccording to the present disclosure. The shift register 1211 illustratedin FIG. 9 and FIG. 10 receives the signal {circle around (9)}illustrated in FIG. 11 as a clock signal (CLK) and the signal {circlearound (4)} with a narrow pulse as the first signal. The shift register1211 further receives the control signal {circle around (10)} (notillustrated in FIG. 11 ) sent by the control circuit 123. In the exampleas illustrated in FIG. 11 , the length of the first signal {circlearound (4)} is N clocks N*CLK, the length of the effective square wavepulse of the first signal {circle around (4)} is M clocks M*CLK, and M=1is taken as an example in FIG. 11 .

Referring to FIG. 10 for details, the M=1-th shift register in the shiftregister 1211 can shift the signal {circle around (4)}, obtain thesignal {circle around (6)} as the first shifted signal (denoted as Firstlatch signal or the like), and output the signal {circle around (6)}.Since the signal {circle around (6)} is output through the nQ outputport of the shift register, the signal {circle around (6)} has anopposite level to the level of the signal {circle around (4)} and isshifted rearward by one CLK. Meanwhile, the Q output port of the N-thshift register in the shift register 1211 further outputs a secondshifted signal (denoted as After shift, or the like). The second shiftedsignal is the signal {circle around (7)} in FIG. 11 . It can be seenthat the signal {circle around (7)} is shifted rearward by N CLKscompared with the signal {circle around (4)}.

In some embodiments, the latch specifically includes an edge triggeredlatch. The edge triggered latch receives the first shifted signal{circle around (6)} and the second shifted signal {circle around (7)} asmentioned above. Specifically, the edge triggered latch generates asignal that the narrow pulse has been removed according to the states ofthe signal {circle around (6)} and the signal {circle around (7)}.

For example, referring to FIG. 11 , when the edge triggered latchdetects the first edge a of the first shifted signal {circle around (6)}(in the present embodiment, the first edge being a falling edge is takenas an example, and the first edge may be an rising edge), the edgetriggered latch outputs a signal with a first level (the first level maybe opposite to the pulse level of the first signal, for example, in thepresent embodiment, the pulse level of the first signal is a high level,and the first level is a low level) through the output end, and keepslatching and outputting the first level until the second edge c of thesecond shifted signal {circle around (7)} is detected. Subsequently,when the edge triggered latch detects the second edge c of the secondshifted signal {circle around (7)} (in the present embodiment, thesecond edge being the falling edge is taken as an example, and thesecond edge may be the rising edge), the edge triggered latch outputsthe signal with the second level through the output end (the secondlevel may be the same as the pulse level of the first signal, forexample, in the present embodiment, the pulse level of the first signalis high level, and the second level is high level), and keeps latchingand outputting the second level until the next detection of the firstedge e of the first shifted signal {circle around (6)}, and so on.Finally, the latch 1212 outputs the signal {circle around (8)} asillustrated in FIG. 11 to the logic processing subcircuit 1213.

The signal {circle around (5)} is obtained by passing the signal {circlearound (8)} through the logic processing subcircuit 1213. Also referringto FIG. 9 and FIG. 11 , for example, the signal {circle around (5)} isobtained by performing a “logical AND” operation on the signal {circlearound (8)} and the signal {circle around (4)}. Then the signal {circlearound (5)} finally output by the final logic processing subcircuit 1213is the second signal after being processed by the entire signalprocessing circuit 121.

In summary, the circuit for signal transmission provided in theembodiment of the present disclosure can, when the external first signalthe is received, process the first signal and output the second signal,which does not include a narrow pulse, to the internal of the memory forprocessing if there is a narrow pulse in the external signal. When thereis no narrow pulse in the external signal, the first signal is directlyoutput to the internal of the memory for processing, thereby eliminatingthe narrow pulse of the external signal received by the memory, so thatthe narrow pulse of the external signal will not affect normalprocessing for the external signal by the memory, and the accuracy ofprocessing the signal by the memory can be improved.

The present disclosure further provides a method for signaltransmission. The method may be performed by the circuit 12 for signaltransmission in the memory 1 as illustrated in FIG. 3 . At this case,the circuit 12 for signal transmission may be understood as a processorby the memory 1, and the method for signal transmission may be performedin a manner of software processing. In particular, the method comprisessteps S1 and S2.

At step S1, a control signal and a first signal are acquired. Thedescription of the control signal and the first signal can be referredto the foregoing embodiments of the present disclosure, and will not beelaborated herein.

At step S2, the first signal is output according to the control signal,or a second signal is obtained by processing the first signal in apreset processing manner according to the control signal, and the secondsignal is output.

In some embodiments, the preset processing manner includes removing anarrow pulse signal between two adjacent pulses in the first signal. Forexample, a signal between two adjacent pulses in the first signal is setto a low level. More specifically, obtaining the second signal byprocessing the first signal according to the preset manner includes:obtaining a first shifted signal by shifting the first signal by M bits,M being the number of second clocks corresponding to a pulse length ofthe first signal; obtaining a second shifted signal by shifting thefirst signal by N bits, N being the number of first clocks correspondingto a cycle of the first signal; and obtaining the second signalaccording to a first edge of the first shifted signal and a second edgeof the second shifted signal.

In some embodiments, the above process of obtaining the second signalaccording to the first edge and the second edge specifically includes:obtaining the second signal by outputting, when a first edge of thefirst shifted signal is detected, a signal with a first level through anoutput end before a second edge of the second shifted signal isdetected, herein the first level is opposite to a level of a pulsesignal of the first signal; and obtaining the second signal byoutputting, when the second edge of the second shifted signal isdetected, a signal with a second level through an output end before thefirst edge of the first shifted signal is detected, herein the secondlevel is same as the level of the pulse signal level of the firstsignal. The specific process may be referred to the process asillustrated in FIG. 11 , and will not be elaborated herein.

In summary, the method for signal transmission method, the circuit, andthe memory provided in the present disclosure can, when the externalfirst signal is received, process the first signal and output the secondsignal, which does not include a narrow pulse, to the internal of thememory for processing if there is a narrow pulse in the external signal.When there is no narrow pulse in the external signal, the first signalis directly output to the internal of the memory for processing, therebyeliminating the narrow pulse of the external signal received by thememory, so that the narrow pulse of the external signal will not affectnormal processing for the external signal by the memory, and theaccuracy of processing the signal by the memory can be improved.

Those ordinary skilled in the art will understand that all or part ofthe steps to implement the above mentioned embodiments of the method maybe accomplished by the hardware related to the program instruction. Theforegoing program may be stored in a computer readable storage medium.When the program is executed, the steps including the above mentionedembodiments of the method are executed. The foregoing storage mediumincludes a Read Only Memory (ROM), a RAM, a magnetic disk, an opticaldisk, or any other medium that can store program codes.

It is to be understood that the above various embodiments are only usedto describe the technical solutions of the present disclosure, and arenot intended to limit the present disclosure. Although the presentdisclosure has been described in detail with reference to the foregoingembodiments, those ordinarily skilled in the art should understand thatthey can still modify the technical solutions described in all theforegoing embodiments, or equivalently replace some or all of thetechnical features, and these modifications or replacements do notdepart the essences of the corresponding technical solutions from thespirit and scope of the technical solutions of all the embodiments ofthe present disclosure.

1. A circuit for signal transmission, comprising: a signal processingcircuit, configured to receive an input first signal, obtain a secondsignal by processing the first signal in a preset processing manner, andtake the second signal as an output signal of the signal processingcircuit; and a selection circuit, configured to receive the input firstsignal, the second signal and a control signal, and take the firstsignal or the second signal as an output signal of the selection circuitaccording to the control signal.
 2. The circuit of claim 1, furthercomprising: a control circuit, configured to send the control signal tothe selection circuit.
 3. The circuit of claim 2, wherein the signalprocessing circuit is further configured to receive the control signal;the signal processing circuit is configured to obtain the second signalby processing the first signal in the preset processing manner when thecontrol signal corresponds to a first state; and the signal processingcircuit is configured to set the second signal to a fixed value when thecontrol signal corresponds to a second state.
 4. The circuit of claim 1,wherein the preset processing manner comprises: setting a signal betweentwo adjacent pulses in the first signal to a low level when the firstsignal is a pulse signal.
 5. The circuit of claim 4, wherein the signalprocessing circuit comprises: a shift register, configured to shift thefirst signal according to a clock cycle of the first signal and outputthe shifted first signal to a latch; the latch, configured to latch areceived signal and output the latched received signal to a logicprocessing subcircuit; and the logic processing subcircuit, configuredto output the second signal according to a received signal.
 6. Thecircuit of claim 5, wherein the shift register comprises: an N-bitserial shift register, wherein N is a number of first clockscorresponding to a cycle of the first signal, and wherein an input endof the N-bit serial shift register is configured to receive the firstsignal; an M-th shift register of the N-bit serial shift register isconfigured to output a first shifted signal, which has been shifted by Mbits, to the latch, wherein M is a number of second clocks correspondingto a pulse length of the first signal; and an output end of the N-bitserial shift register is configured to output a second shifted signal,which has been shifted by N bits, to the latch.
 7. The circuit of claim6, wherein the latch comprises an edge triggered latch; and the edgetriggered latch has a first input end for receiving the first shiftedsignal, a second input end for receiving the second shifted signal, andan output end for outputting a signal, which has been latched, to thelogic processing subcircuit.
 8. The circuit of claim 7, wherein the edgetriggered latch is configured to: output, when a first edge of the firstshifted signal is detected, a signal with a first level through anoutput end before a second edge of the second shifted signal isdetected; and output, when the second edge of the second shifted signalis detected, a signal with a second level through the output end beforethe first edge of the first shifted signal is detected.
 9. The circuitof claim 8, wherein the first level is opposite to a level of a pulsesignal of the first signal; and the second level is the same level asthe level of the pulse signal of the first signal.
 10. The circuit ofclaim 1, wherein the circuit for signal transmission is applied to amemory to receive a first signal from external, and a control circuit isconfigured to: send a control signal corresponding to a first state tothe selection circuit when the memory is in a test state; and send acontrol signal corresponding to a second state to the selection circuitwhen the memory is in a normal operating state.
 11. A memory comprisinga circuit for signal transmission, the circuit comprising: a signalprocessing circuit, configured to receive an input first signal, obtaina second signal by processing the first signal in a preset processingmanner, and take the second signal as an output signal of the signalprocessing circuit; and a selection circuit, configured to receive theinput first signal, the second signal and a control signal, and take thefirst signal or the second signal as an output signal of the selectioncircuit according to the control signal.
 12. The memory of claim 11,further comprising: a control circuit, configured to send the controlsignal to the selection circuit.
 13. The memory of claim 12, wherein thesignal processing circuit is further configured to receive the controlsignal; the signal processing circuit is configured to obtain the secondsignal by processing the first signal in the preset processing mannerwhen the control signal corresponds to a first state; and the signalprocessing circuit is configured to set the second signal to a fixedvalue when the control signal corresponds to a second state.
 14. Thememory of claim 11, wherein the preset processing manner comprises:setting a signal between two adjacent pulses in the first signal to alow level when the first signal is a pulse signal.
 15. The memory ofclaim 14, wherein the signal processing circuit comprises: a shiftregister, configured to shift the first signal according to a clockcycle of the first signal and output the shifted first signal to alatch; the latch, configured to latch a received signal and output thelatched received signal to a logic processing subcircuit; and the logicprocessing subcircuit, configured to output the second signal accordingto a received signal.
 16. The memory of claim 15, wherein the shiftregister comprises: an N-bit serial shift register, wherein N is anumber of first clocks corresponding to a cycle of the first signal, andwherein an input end of the N-bit serial shift register is configured toreceive the first signal; an M-th shift register of the N-bit serialshift register is configured to output a first shifted signal, which hasbeen shifted by M bits, to the latch, wherein M is a number of secondclocks corresponding to a pulse length of the first signal; and anoutput end of the N-bit serial shift register is configured to output asecond shifted signal, which has been shifted by N bits, to the latch.17. A method for signal transmission, comprising: acquiring a controlsignal and a first signal; and outputting the first signal according tothe control signal; or obtaining a second signal by processing the firstsignal in a preset processing manner, and outputting the second signal.18. The method of claim 17, wherein the preset processing mannercomprises: setting a signal between two adjacent pulses in the firstsignal to a low level when the first signal is a pulse signal.
 19. Themethod of claim 18, wherein obtaining the second signal by processingthe first signal in the preset processing manner comprises: obtaining afirst shifted signal by shifting the first signal by M bits, wherein Mis a number of second clocks corresponding to a pulse length of thefirst signal; obtaining a second shifted signal by shifting the firstsignal by N bits, wherein N is a number of first clocks corresponding toa cycle of the first signal; and obtaining the second signal accordingto a first edge of the first shifted signal and a second edge of thesecond shifted signal.
 20. The method of claim 19, wherein obtaining thesecond signal according to the first edge of the first shifted signaland the first edge of the second shifted signal comprises: obtaining thesecond signal by outputting, when a first edge of the first shiftedsignal is detected, a signal with a first level through an output endbefore a second edge of the second shifted signal is detected; whereinthe first level is opposite to a level of a pulse signal of the firstsignal; and obtaining the second signal by outputting, when the secondedge of the second shifted signal is detected, a signal with a secondlevel through an output end before the first edge of the first shiftedsignal is detected; wherein the second level is the same as the level ofthe signal level of the first signal.